Semiconductor module

ABSTRACT

A semiconductor module includes a semiconductor chip having a first surface provided with a first electrode pad and a second surface, opposite to the first surface, provided with a second electrode pad, a first substrate connected to the first electrode pad, a second substrate provided on the side of the second surface, and a conductor section, electrically connecting the second electrode pad and the second substrate, and having a size greater than the second electrode pad in a plan view viewed from the side of the second substrate.

TECHNICAL FIELD

The disclosure relates to a semiconductor module.

This application is based upon and claims priority to Japanese PatentApplication No. 2017-208879, filed on Oct. 30, 2017, the entire contentsof which are incorporated herein by reference.

BACKGROUND ART

Semiconductor modules including a semiconductor chip in which a largecurrent can flow, are used in electric vehicles or the like, and powerapplications or the like. In such semiconductor modules, heat isgenerated when the large current flows, and for this reason, thesemiconductor chip is mounted on one surface of a wiring substrate, anda heat sink for heat dissipation is provided on the other surface of thewiring substrate.

PRIOR ART DOCUMENTS Patent Documents

Patent Document 1: Japanese Laid-Open Patent Publication No. 2012-253125

Patent Document 2: Japanese Laid-Open Patent Publication No. 2014-082233

DISCLOSURE OF THE INVENTION

According to one aspect of the embodiments, a semiconductor moduleincludes a semiconductor chip having a first surface provided with afirst electrode pad, and a second surface, opposite to the firstsurface, provided with a second electrode pad; a first substrateconnected to the first electrode pad; a second substrate provided on theside of the second surface; and a conductor section, electricallyconnecting the second electrode pad and the second substrate, and havinga size greater than the second electrode pad in a plan view viewed fromthe side of the second substrate.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a structure of a semiconductor module.

FIG. 2 is a diagram illustrating a structure of the semiconductor moduleaccording to a first embodiment of the present disclosure.

FIG. 3 is a diagram for explaining the semiconductor module according tothe first embodiment of the present disclosure.

FIG. 4A is a diagram (1) for explaining processes of a method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 4B is a diagram (2) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 5A is a diagram (3) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 5B is a diagram (4) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 6A is a diagram (5) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 6B is a diagram (6) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 7A is a diagram (7) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 7B is a diagram (8) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 8A is a diagram (9) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 8B is a diagram (10) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 9A is a diagram (11) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 9B is a diagram (12) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 10A is a diagram (13) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 10B is a diagram (14) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 11A is a diagram (15) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 11B is a diagram (16) for explaining the processes of the method ofmanufacturing the semiconductor module according to the first embodimentof the present disclosure.

FIG. 12 is a diagram illustrating a structure of the semiconductormodule according to a second embodiment of the present disclosure.

FIG. 13 is a diagram for explaining the semiconductor module accordingto the second embodiment of the present disclosure.

FIG. 14A is a diagram (1) for explaining processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 14B is a diagram (2) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 15A is a diagram (3) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 15B is a diagram (4) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 16A is a diagram (5) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 16B is a diagram (6) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 17A is a diagram (7) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 17B is a diagram (8) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 18A is a diagram (9) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 18B is a diagram (10) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 19A is a diagram (11) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 19B is a diagram (12) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 20A is a diagram (13) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 20B is a diagram (14) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 21A is a diagram (15) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 21B is a diagram (16) for explaining the processes of the method ofmanufacturing the semiconductor module according to the secondembodiment of the present disclosure.

FIG. 22 is a diagram illustrating a structure of the semiconductormodule according to a third embodiment of the present disclosure.

FIG. 23 is a diagram for explaining the semiconductor module accordingto the third embodiment of the present disclosure.

FIG. 24A is a diagram (1) for explaining processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 24B is a diagram (2) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 25A is a diagram (3) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 25B is a diagram (4) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 26A is a diagram (5) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 26B is a diagram (6) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 27A is a diagram (7) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 27B is a diagram (8) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 28A is a diagram (9) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 28B is a diagram (10) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 29A is a diagram (11) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 29B is a diagram (12) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 30A is a diagram (13) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 30B is a diagram (14) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 31A is a diagram (15) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

FIG. 31B is a diagram (16) for explaining the processes of the method ofmanufacturing the semiconductor module according to the third embodimentof the present disclosure.

MODE OF CARRYING OUT THE INVENTION

There are demands to cause a large current to flow in a semiconductormodule, and for this reason, a semiconductor chip in which large currentcan flow, is used and mounted in the semiconductor module. However,because a large amount of heat is generated from the semiconductor chipin which the large current can flow, an efficient heat dissipation isrequired. Hence, there are demands for a semiconductor module that canefficiently dissipate the heat generated from the semiconductor chip.One object of the present disclosure is to efficiently dissipate theheat generated from the semiconductor chip.

According to the present disclosure, it is possible to efficientlydissipate the heat generated from the semiconductor chip.

Embodiments will be described in the following.

DESCRIPTION OF EMBODIMENTS OF PRESENT DISCLOSURE

First, embodiments of the present disclosure will be described in order.In the following description, the same or corresponding elements aredesignated by the same reference numerals, and a repeated description ofsuch elements will be omitted.

[1] A semiconductor module according to one embodiment of the presentdisclosure includes a semiconductor chip having a first surface providedwith a first electrode pad, and a second surface, opposite to the firstsurface, provided with a second electrode pad; a first substrateconnected to the first electrode pad; a second substrate provided on theside of the second surface; and a conductor section, electricallyconnecting the second electrode pad and the second substrate, and havinga size greater than the second electrode pad in a plan view viewed fromthe side of the second substrate.

A semiconductor module, that can cope with high-voltage andhigh-current, uses a semiconductor chip that can cope with high-voltageand high-current, but the semiconductor chip that can cope with thehigh-voltage and high-current generates a large amount of heat andreaches a high temperature when the large current flows. Accordingly, inorder to obtain the semiconductor module that can cope with thehigh-voltage and high-current, it is not only important to use thesemiconductor chip that can cope with the high-voltage and high-current,but extremely important to dissipate heat from the semiconductor module.In other words, as the requirements for the semiconductor chip to copewith the high-voltage and high-current become more severe, the moreimportant the heat dissipation from the semiconductor chip becomes. As aresult of intensive studies conducted by the present inventors, asemiconductor module having a structure with an improved heatdissipation efficiency was conceived, capable of dissipating heat fromboth surfaces of the semiconductor chip. The disclosure of thisapplication is based on such findings and conceptions of the presentinventors.

[2] The size of the conductor section is greater than the semiconductorchip in the plan view viewed from the side of the second substrate.

[3] A third electrode pad is provided on the second surface, the firstelectrode terminal is electrically connected to the third electrode pad,and the first electrode terminal has a flat shape, and is set parallelto the first substrate and the second substrate, between the firstsubstrate and the second substrate.

[4] The conductor section and the third electrode pad overlap in theplan view viewed from the side of the second substrate.

[5] A frame section, formed by a material different from that of theconductor section, is provided on a portion of a periphery of theconductor section.

[6] A metal plate is electrically connected to the second electrode padthat is provided on the second surface of the semiconductor chip, andthe metal plate and the conductor section are electrically connected.

[7] A second electrode terminal is electrically connected to the secondelectrode pad that is provided on the second surface of thesemiconductor chip, and the second electrode terminal and the conductorsection are electrically connected.

[8] The semiconductor chip is formed by a material including SiC.

DETAILS OF EMBODIMENTS OF PRESENT DISCLOSURE

The embodiment of the present disclosure will be described in detail inthe following, however, the present disclosure is not limited to theseembodiments.

First Embodiment

First, the above-mentioned semiconductor module will be described inmore detail, by referring to FIG. 1. The semiconductor moduleillustrated in FIG. 1 includes a semiconductor chip 910 mounted on acircuit board 920. The circuit board 920 includes an interconnect layer922 a formed on a first surface 920 a that forms one surface of aninsulating substrate 921, and a heat dissipation layer 923 formed on asecond surface 920 b that forms the other surface of the insulatingsubstrate 921. The semiconductor chip 910 is mounted on the interconnectlayer 922 a, and the heat dissipation layer 923 is connected to a heatsink that is not illustrated.

The semiconductor chip 910 includes a drain electrode pad 911 providedon a first surface 910 a that is one surface, and a source electrode pad912 and a gate electrode pad 913 provided on a second surface 910 b thatis the other surface.

Accordingly, the interconnect layer 922 a provided on the first surface920 a of the circuit board 920, and the drain electrode pad 911 providedon the first surface 910 a of the semiconductor chip 910, areelectrically connected by a solder or the like that is not illustrated.In addition, the source electrode pad 912 provided on the second surface910 b of the semiconductor chip 910 is electrically connected to theinterconnect layer 922 b provided on the first surface 920 a of thecircuit board 920 by a bonding wire 931. The gate electrode pad 913provided on the second surface 910 b of the semiconductor chip 910 iselectrically connected to an interconnect layer 922 c provided on thefirst surface 920 a of the circuit board 920 by a bonding wire 932. Anelectrode terminal 941 is electrically connected to the interconnectlayer 922 b by a solder or the like that is not illustrated, and anelectrode terminal 942 is electrically connected to the interconnectlayer 922 c by a solder or the like that is not illustrated. On the sideof the first surface 920 a of the circuit board 920 in the semiconductormodule illustrated in FIG. 1, the entire semiconductor chip 910 iscovered by a resin material 970.

In the semiconductor module illustrated in FIG. 1, heat generated fromthe semiconductor chip 910 is dissipated by the heat sink that is notillustrated, via the heat dissipation layer 923 of the circuit board 920that is provided on the side of the first surface 910 a of thesemiconductor chip 910.

There are demands for the semiconductor module of the type describedabove to cope with high-voltage and high-current, and for this reason,the semiconductor chip 910 that is used also copes with the high-voltageand high-current. The semiconductor chip 910 that can cope with thehigh-voltage and high-current includes a semiconductor chip using Si asthe semiconductor material, and semiconductor chips using SiC or thelike as the semiconductor material. Because SiC has a wider band gapwhen compared to that of Si, SiC is suited for use as the semiconductormaterial when coping with the high-voltage and high-current.

However, in general, when the current flowing in the semiconductor chip910 increases, the heat generated from the semiconductor chip 910increases, and there are cases where the heat dissipation may becomeinsufficient according to the semiconductor module having the structureillustrated in FIG. 1. In other words, even when it is possible toobtain the semiconductor chip that can cope with the high-voltage andhigh-current, there are cases where this semiconductor chip cannot beused in the semiconductor module from a viewpoint of providingsufficient heat dissipation.

A semiconductor module according to this embodiment has a structure thatcan provide sufficient heat dissipation, even when the semiconductorchip that can cope with the high-voltage and high-current is used in thesemiconductor module.

(Semiconductor Module)

Next, the semiconductor module according to this embodiment will bedescribed, by referring to FIG. 2. The semiconductor module according tothis embodiment includes a semiconductor chip 10, that is asemiconductor element, a first substrate 20, a second substrate 30, orthe like.

The semiconductor chip 10 is formed by Si or SiC, and a drain electrodepad 11 is formed on a first surface 10 a that forms one surface, and asource electrode pad 12 and a gate electrode pad 13 are formed on asecond surface 10 b that forms the other surface. From a viewpoint ofefficiency and reduced size, the semiconductor chip 10 is preferablyformed by SiC. In this application, the drain electrode may be referredto as a first electrode, the source electrode may be referred to as asecond electrode, and the gate electrode may be referred to as a thirdelectrode. In this embodiment, a description will be given for the casewhere the semiconductor chip 10 is a Field Effect Transistor (FET),however, the semiconductor chip 10 may be a transistor. In the casewhere the semiconductor chip 10 is the transistor, a collector electrodeforms the first electrode, an emitter electrode forms the secondelectrode, and a base electrode forms the third electrode.

The first substrate 20 includes an insulating substrate 21 formed by aninsulator, a metal layer 22 forming an interconnect layer formed on afirst surface 20 a that forms one surface, and a metal layer 23 forminga heat dissipation layer formed on a second surface 20 b that forms theother surface. The drain electrode pad 11 of the semiconductor chip 10is electrically connected to the metal layer 22 formed on the firstsurface 20 a of the first substrate 20, by a solder or the like that isnot illustrated.

The second substrate 30 includes an insulating substrate 31 formed by aninsulator, a metal layer 32 forming an interconnect layer formed on afirst layer 30 a that forms one surface, and a metal layer 33 forming aheat dissipation layer formed on a second surface 30 b that forms theother surface.

The insulating substrate 21 and the insulating substrate 31 are formedby an insulating material, such as ceramics or the like, and the metallayers 22, 23, 32, and 33 are formed by copper (Cu) or the like.

A gate electrode terminal 50 is electrically connected to the gateelectrode pad 13 of the semiconductor chip 10 by a solder or the likethat is not illustrated. The gate electrode terminal 50 is formed to anelongated flat shape by copper (Cu) or the like, and is electricallyconnected to the gate electrode pad 13 in a state where the gateelectrode terminal 50 is arranged between the first substrate 20 and thesecond substrate 30, and parallel to the first substrate 20 and thesecond substrate 30. In this application, the gate electrode terminal 50may be referred to as a first electrode terminal. In addition, in thisspecification, the term parallel state does not refer to a strictlyparallel state, geometrically, and may include a tolerable dimensionalerror or the like generated during manufacture, such that the parallelstate has a range with which effects of the present invention areobtainable.

The semiconductor chip 10 is covered by resin layers 71 and 72 that areformed by an insulating resin material, excluding a region formed withthe source electrode pad 12. A source conductor section 40, made of aconductive material, such as a metal material or the like, for example,is formed on the source electrode pad 12 of the semiconductor chip 10.The source conductor section 40 is electrically connected to the sourceelectrode pad 12 of the semiconductor chip on one side 40 a thereof, andis electrically connected to the metal layer 32 on the first surface 30a of the second substrate 30 on the other side 40 b thereof. The sourceconductor section 40 is formed by a highly conductive material which, ingeneral, also has a high thermal conductivity. Accordingly, the sourceconductor section 40 electrically connects the source electrode pad 12of the semiconductor chip 10 and the metal layer 32 of the secondsubstrate 30, and heat generated from the semiconductor chip 10 can beefficiently dissipated to the second substrate 30 via the sourceconductor section 40.

The source conductor section 40 is formed so that the other side 40 bconnected to the metal layer 32 on the first surface 30 a of the secondsubstrate 30 has an area greater than an area of the one side 40 aconnected to the source electrode pad 12 of the semiconductor chip 10.More particularly, the area of the other side 40 b of the sourceconductor section 40 is greater than the area of the semiconductor chip10, and the entire semiconductor chip 10 is covered by the sourceconductor section 40, above the semiconductor chip 10. Accordingly, thegate electrode pad 13 of the semiconductor chip 10 is covered by thesource conductor section 40 above the gate electrode pad 13.

FIG. 3 illustrates a positional relationship between the semiconductorchip 10 and the source conductor section 40 in the plan view viewed fromthe side of the second substrate 30, in the semiconductor moduleaccording to this embodiment. In FIG. 3, the illustration of the secondsubstrate 30, the gate electrode terminal 50, the resin layer 72, or thelike is omitted for the sake of convenience. In the semiconductor moduleaccording to this embodiment, the entire semiconductor chip 10 iscovered by the source conductor section 40 in the plan view viewed fromthe side of the second substrate 30. Accordingly, the gate electrode pad13 of the semiconductor chip 10 is also covered by the source conductorsection 40. In this embodiment, the semiconductor chip 10 has a sizethat is approximately 10 mm×approximately 10 mm when the semiconductormaterial is Si, and a size that is approximately 5 mm×approximately 5 mmwhen the semiconductor material is SiC, and the size of the sourceconductor section 40 in the plan view is approximately 15mm×approximately 20 mm.

As will be described later, the source conductor section 40 is formed bysintering a silver paste or the like, and thus, a frame section 41 forforming the source conductor section 40 is provided on a portion in aperiphery of the source conductor section 40. Because the frame section41 is for forming the source conductor section 40, normally, the framesection 41 is formed by a material different from that of the sourceconductor section 40. The frame section 41 may be formed by aninsulator, or a metal or the like. In addition, the semiconductor moduleaccording to this embodiment may have a structure in which this framesection 41 is removed. Further, a periphery of the frame section 41 orthe like, between the first substrate 20 and the second substrate 30, isbound by the insulating resin layer 71 and the insulating resin layer72, and an insulating resin section 73 that is formed by an insulatingresin material.

In the semiconductor module according to this embodiment, a heat sinkthat is not illustrated is connected to the metal layer 23 on the secondsurface 20 b of the first substrate 20, and similarly, a heat sink thatis not illustrated is connected to the metal layer 33 on the secondsurface 30 b of the second substrate 30. Accordingly, the heat generatedfrom the semiconductor chip 10 is dissipated from the first surface 10 aof the semiconductor chip 10 to the heat sink that is not illustratedvia the first substrate 20, and is dissipated from the second surface 10b of the semiconductor chip 10 to the heat sink that is not illustratedvia the second substrate 30.

In the semiconductor module illustrated in FIG. 1, the heat generatedfrom the semiconductor chip can only be dissipated from the firstsurface 910 a of the semiconductor chip 910, that is, only from onesurface. In the semiconductor module according to this embodiment,however, the heat generated from the semiconductor chip can bedissipated from both the first surface 10 a and the second surface 10 bof the semiconductor chip. For this reason, compared to thesemiconductor module having the structure illustrated in FIG. 1, thesemiconductor module according to this embodiment can improve the heatdissipation efficiency of the semiconductor chip.

In addition, the source conductor section 40 that is electricallyconnected to the source electrode pad 12 on the second surface 10 b ofthe semiconductor chip 10 has a large area and a low thermal resistance,and thus, it is possible to efficiently dissipate the heat on the sideof the second surface 10 b of the semiconductor chip 10.

Further, according to this embodiment, the gate electrode terminal 50 isdirectly and electrically connected to the gate electrode pad 13 of thesemiconductor chip 10, the source conductor section 40 is directly andelectrically connected to the source electrode pad 12, and no bondingwire is used. Hence, it is unnecessary to secure a region for formingthe bonding wire, and a thickness of the semiconductor module can bereduced. In other words, it is possible to arrange the first substrate20 and the second substrate 30 close to each other. By reducing thethickness of the semiconductor module, it is not only possible to reducethe size of the semiconductor module, but also reduce a height of thesource conductor section 40. For this reason, a distance from thesemiconductor chip 10 to the second substrate 20 can be shortened, tofurther improve the heat dissipation performance.

(Method of Manufacturing Semiconductor Module)

Next, a method of manufacturing the semiconductor module according tothis embodiment will be described, by referring to FIG. 4A through FIG.11B. FIG. 4A through FIG. 11A are top views, and FIG. 4B through FIG.11B are cross sectional views.

First, as illustrated in FIG. 4A and FIG. 4B, the drain electrode pad 11formed on the first surface 10 a of the semiconductor chip 10 is bondedto the metal layer 22 forming the interconnect layer on the firstsurface 20 a of the first substrate 20, by a solder or the like that isnot illustrated. Hence, the metal layer 22 of the first substrate 20 andthe drain electrode pad 11 of the semiconductor chip 10 are electricallyconnected. The solder that is used to electrically connect the metallayer 22 and the drain electrode pad 11 is a solder including SuSb orthe like, and a bonding temperature of this solder is approximately 250°C.

Next, as illustrated in FIG. 5A and FIG. 5B, the resin layer 71including an opening 71 a is formed in a region on the second surface 10b of the semiconductor chip 10 where the source electrode pad 12 and thegate electrode pad 13 are formed. The resin layer 71 is formed by aninsulating material. More particularly, a resist pattern, that is notillustrated and including an opening in a region where the resin layer71 is formed, is formed, and a resin material for forming the resinlayer 71 is coated thereon. The resist pattern is formed by a materialthat repels this resin material, and the resin material adhered on theresist pattern is repelled. Thereafter, the resist pattern that is notillustrated is removed by an organic solvent or the like, and the resinmaterial is cured by applying heat, to form the insulating resin layer71. In this case, the resin material that is used for the resin layer 71is an epoxy resin, for example, and a curing temperature of the epoxyresin is approximately 200° C. Hence, the resin layer 71, including theopening 71 a, is formed. The resin layer 71 covers the entire surface ofthe semiconductor chip 10, excluding the region where the opening 71 ais formed, and the resin layer 71 also covers a portion of the metallayer 22 in the periphery of the semiconductor chip 10. The resin layer71 is formed to a height that is approximately the same as those of thesource electrode pad 12 and the gate electrode pad 13 on the secondsurface 10 b of the semiconductor chip 10.

Next, as illustrated in FIG. 6A and FIG. 6B, the gate electrode terminal50 is bonded to the gate electrode pad 13 by a solder or the like.Hence, the gate electrode pad 13 and the gate electrode terminal 50 areelectrically connected. The gate electrode terminal 50 is formed to theelongated flat shape, and in a state where the gate electrode terminal50 is arranged on the resin layer 71, a vicinity of one end part isbonded to the gate electrode pad 13, and the other end part extends to avicinity of the left side of the first substrate 20 in FIG. 6A and FIG.6B. The solder that is used to electrically connect the gate electrodeterminal 50 and the gate electrode pad 13 is a solder including SuCu orthe like, and a bonding temperature of this solder is approximately 230°C.

Next, as illustrated in FIG. 7A and FIG. 7B, the resin layer 72 isformed on the resin layer 71, and the gate electrode terminal 50 on theresin layer 71. The resin layer 72 is formed by an insulating material.More particularly, a resist pattern, that is not illustrated andincluding an opening in a region where the resin layer 72 is formed, isformed, and a resin material for forming the resin layer 72 is coatedthereon. The resist pattern is formed by a material that repels thisresin material, and the resin material adhered on the resist pattern isrepelled. Thereafter, the resist pattern that is not illustrated isremoved by an organic solvent or the like, and the resin material iscured by applying heat, to form the insulating resin layer 72. The resinmaterial that is used for the resin layer 72 is an epoxy resin, forexample, and the curing temperature of the epoxy resin is approximately200° C. Hence, the resin layer 72 is formed on the resin layer 71, andthe gate electrode terminal 50 on the insulating layer 71. An opening 72a in the resin layer 72 covers the gate electrode terminal 50, and isnarrower than the opening 71 a in the resin layer 71, and thus, thesource electrode pad 12 on the second surface 10 b of the semiconductorchip 10 is exposed at the opening 72 a in the resin layer 72 and theopening 71 a in the resin layer 71. The resin layer 72 is formed to havea height of approximately 3 mm to approximately 4 mm from the secondsurface 10 b of the semiconductor chip 10.

Next, as illustrated in FIG. 8A and FIG. 8B, the frame section 41 isbonded onto the resin layer 72. The frame section 41 includes an opening41 a having a size of 15 mm×20 mm, and is bonded to the resin layer 72by an adhesive that is not illustrated, so that the semiconductor chip10 is positioned inside the opening 41 a in the frame section 41 in theplan view. The frame section 41 may be formed by an insulator, or aconductor such as a metal or the like.

Next, as illustrated in FIG. 9A and FIG. 9B, the source conductorsection 40 is formed inside the opening 41 a in the frame section 41.More particularly, a fluid material, such as a silver paste or the likeforming the source conductor section 40, is cast inside the opening 41 ain the frame section 41 and solidified by sintering, to form the sourceconductor section 40. Accordingly, the source conductor section 40, thatelectrically connects to the source electrode pad 12 of thesemiconductor chip 10, is formed. The source conductor section 40 thatis formed in this manner covers above the semiconductor chip 10, and thesource conductor section 40 and the semiconductor chip 10 overlap in theplan view. Hence, in the plan view, the gate electrode pad 13 of thesemiconductor chip 10 also overlaps the source conductor section 40.Although the height of the source conductor section 40 that is formed is10 mm to 20 mm, the low height is advantageous from a viewpoint of heatdissipation. Although the frame section 41 may be removed, the framesection 41 need not be removed when no problems exist from a practicalviewpoint.

Next, as illustrated in FIG. 10A and FIG. 10B, the metal layer 32 on thefirst surface 30 a of the second substrate 30 is bonded onto the sourceconductor section 40 by a solder or the like. Hence, the sourceconductor section 40 and the metal layer 32 of the second substrate 30are electrically connected, and the source electrode pad 12 of thesemiconductor chip 10 and the metal layer 32 of the second substrate 30are electrically connected via the source conductor section 40. Abonding temperature in this case is approximately 180° C.

Next, as illustrated in FIG. 11A and FIG. 11B, a space between the firstsubstrate 20 and the second substrate 30 is filled with the insulatingresin section 73. More particularly, a fluid resin material for formingthe insulating resin section 73 is cast between the first substrate 20and the second substrate 30, and cured at a temperature of approximately140° C. by applying heat, to form the insulating resin section 73. Theinsulating resin section 73 is formed to fill the space between thefirst substrate 20 and the second substrate 30, but exposes a portion ofthe gate electrode terminal 50.

The semiconductor module according to this embodiment can bemanufactured by the processes described above.

Second Embodiment

Next, the semiconductor module according to a second embodiment will bedescribed, by referring to FIG. 12. The semiconductor module accordingto this embodiment includes a source metal plate 140 bonded on thesource electrode pad 12 of the semiconductor chip 10, and the sourceconductor section 40 is formed on the source metal plate 140.Accordingly, the source electrode pad 12 and the source metal plate 140are electrically connected, and the source metal plate 140 and thesource conductor section 40 are electrically connected. FIG. 13illustrates a positional relationships of the semiconductor chip 10, thesource metal plate 140, and the source conductor section 40 in the planview viewed from the side of the second substrate 30. In FIG. 13, theillustration of the second substrate 30, the gate electrode terminal 50,the resin layer 72, or the like is omitted for the sake of convenience.The source metal plate 140 is formed by copper or the like, and isformed to a rectangular shape having a size greater than that of thesource electrode pad 12 of the semiconductor chip 10. In thisembodiment, the heat dissipation efficiency is improved by the provisionof the source metal plate 140.

(Method of Manufacturing Semiconductor Module)

Next, a method of manufacturing the semiconductor module according tothis embodiment will be described, by referring to FIG. 14A through FIG.21B. FIG. 14A through FIG. 21A are top views, and FIG. 14B through FIG.21B are cross sectional views.

First, as illustrated in FIG. 14A and FIG. 14B, the drain electrode pad11, that is formed on the first surface 10 a of the semiconductor chip10, is bonded on the metal layer 22 forming the interconnect layer onthe first surface 20 a of the first substrate 20, by a solder or thelike that is not illustrated.

Next, as illustrated in FIG. 15A and FIG. 15B, the resin layer 71,including the opening 71 a, is formed in the region on the secondsurface 10 b of the semiconductor chip 10 where the source electrode pad12 and the gate electrode pad 13 are formed.

Next, as illustrated in FIG. 16A and FIG. 16B, the gate electrodeterminal 50 is bonded to the gate electrode pad 13 by a solder or thelike, and the source metal plate 140 is bonded to the source electrodepad 12 by a solder or the like.

Next, as illustrated in FIG. 17A and FIG. 17B, the resin layer 72 isformed on the resin layer 71, and the gate electrode terminal 50 on theresin layer 71.

Next, as illustrated in FIG. 18A and FIG. 18B, the frame section 41,including the opening 41 a, is bonded onto the resin layer 72.

Next, as illustrated in FIG. 19A and FIG. 19B, the source conductorsection 40 is formed inside the opening 41 a in the frame section 41.Hence, the source conductor section 40 is formed on the source metalplate 140.

Next, as illustrated in FIG. 20A and FIG. 20B, the metal layer 32 on thefirst surface 30 a of the second substrate 30 is bonded onto the sourceconductor section 40 by a solder or the like.

Next, as illustrated in FIG. 21A and FIG. 21B, the space between thefirst substrate 20 and the second substrate 30 is filled with theinsulating resin section 73.

The semiconductor module according to this embodiment can bemanufactured by the processes described above.

Unless otherwise indicated, the features of this embodiment are the sameas those of the first embodiment.

Third Embodiment

Next, the semiconductor module according to a third embodiment will bedescribed, by referring to FIG. 22. The semiconductor module accordingto this embodiment includes a source auxiliary terminal 240 bonded onthe source electrode pad 12 of the semiconductor chip 10, and the sourceconductor section 40 is formed on the source auxiliary terminal 240.Accordingly, the source electrode pad 12 and the source auxiliaryterminal 240 are electrically connected, and the source auxiliaryterminal 240 and the source conductor section 40 are electricallyconnected. In this application, the source auxiliary terminal 240 may bereferred to as a second electrode terminal.

FIG. 23 illustrates positional relationships of the semiconductor chip10, the gate electrode terminal 50, the source auxiliary terminal 240,and the source conductor section 40, in the plan view viewed from theside of the second substrate 30. In FIG. 23, the illustration of thesecond substrate 30, the resin layer 72, or the like is omitted for thesake of convenience. The source auxiliary terminal 240 is formed bycopper or the like, and is formed to a shape that is greater than thatof the source electrode pad 12 of the semiconductor chip 10. The sourceauxiliary terminal 240 is provided separately from the source electrode,and is provided to apply a stable gate voltage in the semiconductor chipin which a large current flows. Similar to the gate electrode terminal50, the source auxiliary terminal 240 is arranged between the firstsubstrate 20 and the second substrate 30, parallel to the firstsubstrate 20 and the second substrate 30, and a portion of the end partof the source auxiliary terminal 240 is exposed from the insulatingresin section 73. In this embodiment, it is possible to improve the heatdissipation efficiency and stabilize the semiconductor module, by theprovision of the source auxiliary terminal 240.

(Method of Manufacturing Semiconductor Module)

Next, a method of manufacturing the semiconductor module according tothis embodiment will be described, by referring to FIG. 24A through FIG.31B. FIG. 24A through FIG. 31A are top views, and FIG. 24B through FIG.31B are cross sectional views.

First, as illustrated in FIG. 24A and FIG. 24B, the drain electrode pad11, that is formed on the first surface 10 a of the semiconductor chip10, is bonded on the metal layer 22 forming the interconnect layer onthe first surface 20 a of the first substrate 20, by a solder or thelike that is not illustrated.

Next, as illustrated in FIG. 25A and FIG. 25B, the resin layer 71,including the opening 71 a, is formed in the region on the secondsurface 10 b of the semiconductor chip 10 where the source electrode pad12 and the gate electrode pad 13 are formed.

Next, as illustrated in FIG. 26A and FIG. 26B, the gate electrodeterminal 50 is bonded to the gate electrode pad 13 by a solder or thelike, and the source auxiliary terminal 240 is bonded to the sourceelectrode pad 12 by a solder or the like.

Next, as illustrated in FIG. 27A and FIG. 27B, the resin layer 72 isformed on the resin layer 71, and the gate electrode terminal 50 on theresin layer 71.

Next, as illustrated in FIG. 28A and FIG. 28B, the frame section 41,including the opening 41 a, is bonded onto the resin layer 72.

Next, as illustrated in FIG. 29A and FIG. 29B, the source conductorsection 40 is formed inside the opening 41 a in the frame section 41.Hence, the source conductor section 40 is formed on the source metalplate 140.

Next, as illustrated in FIG. 30A and FIG. 30B, the metal layer 32 on thefirst surface 30 a of the second substrate 30 is bonded onto the sourceconductor section 40 by a solder or the like.

Next, as illustrated in FIG. 31A and FIG. 31B, the space between thefirst substrate 20 and the second substrate 30 is filled with theinsulating resin section 73.

The semiconductor module according to this embodiment can bemanufactured by the processes described above.

Unless otherwise indicated, the features of this embodiment are the sameas those of the first embodiment.

Although the embodiments are described in detail above, the presentinvention is not limited to the particular embodiments, and variousvariations and modifications may be made without departing from thescope of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

-   -   10 Semiconductor chip    -   10 a First surface    -   10 b Second surface    -   11 Drain electrode pad    -   12 Source electrode pad    -   13 Gate electrode pad    -   20 First substrate    -   20 a First surface    -   20 b Second surface    -   21 Insulating substrate    -   22 Metal layer    -   23 Metal layer    -   30 Second substrate    -   30 a First surface    -   30 b Second surface    -   31 Insulating substrate    -   32 Metal layer    -   33 Metal layer    -   40 Source conductor section    -   40 a One side    -   40 b Other side    -   41 Frame section    -   41 a Opening    -   50 Gate electrode terminal    -   71 Resin layer    -   71 a Opening    -   72 Resin layer    -   72 a Opening    -   73 Insulating resin section    -   140 Source metal plate    -   240 Source auxiliary terminal    -   910 Semiconductor chip    -   910 a First surface    -   910 b Second surface    -   911 Drain electrode pad    -   912 Source electrode pad    -   913 Gate electrode pad    -   920 Circuit board    -   920 a First surface    -   920 b Second surface    -   921 Insulating substrate    -   922 a Interconnect layer    -   922 b Interconnect layer    -   922 c Interconnect layer    -   923 Heat dissipation layer    -   931 Bonding wire    -   932 Bonding wire    -   941 Electrode terminal    -   942 Electrode terminal    -   970 Resin material

1. A semiconductor module comprising: a semiconductor chip having afirst surface provided with a first electrode pad, and a second surface,opposite to the first surface, provided with a second electrode pad; afirst substrate connected to the first electrode pad; a second substrateprovided on the side of the second surface; and a conductor section,electrically connecting the second electrode pad and the secondsubstrate, and having a size greater than the second electrode pad in aplan view viewed from the side of the second substrate.
 2. Thesemiconductor module as claimed in claim 1, wherein the size of theconductor section is greater than the semiconductor chip in the planview viewed from the side of the second substrate.
 3. The semiconductormodule as claimed in claim 1, further comprising: a third electrode padprovided on the second surface, wherein the first electrode terminal iselectrically connected to the third electrode pad, and wherein the firstelectrode terminal has a flat shape, and is set parallel to the firstsubstrate and the second substrate, between the first substrate and thesecond substrate.
 4. The semiconductor module as claimed in claim 3,wherein the conductor section and the third electrode pad overlap in theplan view viewed from the side of the second substrate.
 5. Thesemiconductor module as claimed in claim 1, further comprising: a framesection, formed by a material different from that of the conductorsection, provided on a portion of a periphery of the conductor section.6. The semiconductor module as claimed in claim 1, further comprising: ametal plate electrically connected to the second electrode pad that isprovided on the second surface of the semiconductor chip, wherein themetal plate and the conductor section are electrically connected.
 7. Thesemiconductor module as claimed in claim 1, further comprising: a secondelectrode terminal electrically connected to the second electrode padthat is provided on the second surface of the semiconductor chip,wherein the second electrode terminal and the conductor section areelectrically connected.
 8. The semiconductor module as claimed in claim1, wherein the semiconductor chip is formed by a material including SiC.9. The semiconductor module as claimed in claim 2, further comprising: athird electrode pad is provided on the second surface, wherein the firstelectrode terminal is electrically connected to the third electrode pad,and wherein the first electrode terminal has a flat shape, and is setparallel to the first substrate and the second substrate, between thefirst substrate and the second substrate.
 10. The semiconductor moduleas claimed in claim 9, wherein the conductor section and the thirdelectrode pad overlap in the plan view viewed from the side of thesecond substrate.
 11. The semiconductor module as claimed in claim 9,further comprising: a frame section, formed by a material different fromthat of the conductor section, provided on a portion of a periphery ofthe conductor section.
 12. The semiconductor module as claimed in claim9, further comprising: a metal plate electrically connected to thesecond electrode pad that is provided on the second surface of thesemiconductor chip, wherein the metal plate and the conductor sectionare electrically connected.
 13. The semiconductor module as claimed inclaim 9, further comprising: a second electrode terminal electricallyconnected to the second electrode pad that is provided on the secondsurface of the semiconductor chip, wherein the second electrode terminaland the conductor section are electrically connected.
 14. Thesemiconductor module as claimed in claim 9, wherein the semiconductorchip is formed by a material including SiC.
 15. The semiconductor moduleas claimed in claim 2, further comprising: a frame section, formed by amaterial different from that of the conductor section, provided on aportion of a periphery of the conductor section.
 16. The semiconductormodule as claimed in claim 2, further comprising: a metal plateelectrically connected to the second electrode pad that is provided onthe second surface of the semiconductor chip, wherein the metal plateand the conductor section are electrically connected.
 17. Thesemiconductor module as claimed in claim 2, further comprising: a secondelectrode terminal electrically connected to the second electrode padthat is provided on the second surface of the semiconductor chip,wherein the second electrode terminal and the conductor section areelectrically connected.
 18. The semiconductor module as claimed in claim1, wherein the first substrate is configured to connect to a first heatsink to dissipate heat generated from the semiconductor chip via thefirst surface, and the second substrate is configured to connect to asecond heat sink to dissipate heat generated from the semiconductor chipvia the second surface.
 19. The semiconductor module as claimed in claim3, wherein the first substrate is configured to connect to a first heatsink to dissipate heat generated from the semiconductor chip via thefirst surface, and the second substrate is configured to connect to asecond heat sink to dissipate heat generated from the semiconductor chipvia the second surface.
 20. The semiconductor module as claimed in claim5, wherein the first substrate is configured to connect to a first heatsink to dissipate heat generated from the semiconductor chip via thefirst surface, and the second substrate is configured to connect to asecond heat sink to dissipate heat generated from the semiconductor chipvia the second surface.